`include "chunjun_define.sv" 
`include "chunjun_lib_define.sv" 
`define CHUNJUN_CORE_N 1

module chunjun_mem_wrap_top (
  input  logic                                                                                clk     ,
  input  logic                                                                                rst_n   ,
  // DCache Tag RAM
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0]                                   dcu_ram_tag_cs   ,
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0]                                   dcu_ram_tag_wr   ,
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_SETIDX_W-1:0]         dcu_ram_tag_addr ,
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_TAG_RAM_DATA_W-1:0]   dcu_ram_tag_wen  ,
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_TAG_RAM_DATA_W-1:0]   dcu_ram_tag_wdata,
  output logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_TAG_RAM_DATA_W-1:0]   dcu_ram_tag_rdata,
  // DCache Data0 RAM
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0]                                   dcu_ram_data0_cs   ,
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0]                                   dcu_ram_data0_wr   ,
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_ADDR_W-1:0]  dcu_ram_data0_addr ,
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_DATA_W-1:0]  dcu_ram_data0_wen  ,
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_DATA_W-1:0]  dcu_ram_data0_wdata,
  output logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_DATA_W-1:0]  dcu_ram_data0_rdata,
  // DCache Data1 RAM
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0]                                   dcu_ram_data1_cs   ,
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0]                                   dcu_ram_data1_wr   ,
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_ADDR_W-1:0]  dcu_ram_data1_addr ,
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_DATA_W-1:0]  dcu_ram_data1_wen  ,
  input  logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_DATA_W-1:0]  dcu_ram_data1_wdata,
  output logic [`CHUNJUN_CORE_N-1:0][4-1:0][`CHUNJUN_DC_DATA_RAM_DATA_W-1:0]  dcu_ram_data1_rdata

);


for (genvar i=0; i<`CHUNJUN_CORE_N; i++) begin: g_all_dc_ram
  for(genvar j=0; j<4; j++) begin : g_dc_ram

    sram_wrap #(
      .DEPTH  ( `CHUNJUN_DC_SET_N          ),
      .DATA_W ( `CHUNJUN_DC_TAG_RAM_DATA_W )
    ) u_dc_tag_ram (
      .clk      ( clk                     ),
      .rst_n    ( rst_n                   ),
      .mem_ctrl ( mem_ctrl                ),
      .mem_dft  ( mem_dft                 ),
      .mem_lp   ( mem_lp                  ),
      .scan_en  ( dft_icg_scan_en         ),
      .cs       ( dcu_ram_tag_cs[i][j]    ),
      .wr       ( dcu_ram_tag_wr[i][j]    ),
      .addr     ( dcu_ram_tag_addr[i][j]  ),
      .wdata    ( dcu_ram_tag_wdata[i][j] ),
      .wen      ( dcu_ram_tag_wen[i][j]   ),
      .rdata    ( dcu_ram_tag_rdata[i][j] )
    );

    sram_wrap #(
      .DEPTH  ( `CHUNJUN_DC_DATA_RAM_DEPTH_N ),
      .DATA_W ( `CHUNJUN_DC_DATA_RAM_DATA_W  )
    ) u_dc_data0_ram (
      .clk      ( clk                       ),
      .rst_n    ( rst_n                     ),
      .mem_ctrl ( mem_ctrl                  ),
      .mem_dft  ( mem_dft                   ),
      .mem_lp   ( mem_lp                    ),
      .scan_en  ( dft_icg_scan_en           ),
      .cs       ( dcu_ram_data0_cs[i][j]    ),
      .wr       ( dcu_ram_data0_wr[i][j]    ),
      .addr     ( dcu_ram_data0_addr[i][j]  ),
      .wdata    ( dcu_ram_data0_wdata[i][j] ),
      .wen      ( dcu_ram_data0_wen[i][j]   ),
      .rdata    ( dcu_ram_data0_rdata[i][j] )
    );

    sram_wrap #(
      .DEPTH  ( `CHUNJUN_DC_DATA_RAM_DEPTH_N ),
      .DATA_W ( `CHUNJUN_DC_DATA_RAM_DATA_W  )
    ) u_dc_data1_ram (
      .clk      ( clk                       ),
      .rst_n    ( rst_n                     ),
      .mem_ctrl ( mem_ctrl                  ),
      .mem_dft  ( mem_dft                   ),
      .mem_lp   ( mem_lp                    ),
      .scan_en  ( dft_icg_scan_en           ),
      .cs       ( dcu_ram_data1_cs[i][j]    ),
      .wr       ( dcu_ram_data1_wr[i][j]    ),
      .addr     ( dcu_ram_data1_addr[i][j]  ),
      .wdata    ( dcu_ram_data1_wdata[i][j] ),
      .wen      ( dcu_ram_data1_wen[i][j]   ),
      .rdata    ( dcu_ram_data1_rdata[i][j] )
    );
  end
end


endmodule

`include "chunjun_undefine.sv" 